The present invention relates to semiconductor integrated circuits. More particularly, the present invention relates to MOSFET technology for programmable address decode and correction.
Many electronic products use memory devices to store data. Non-volatile memory, such as electrically programmable read-only memory (EPROM) and electrically-erasable programmable read-only memory (EEPROM), are extensively used for storing data in, for example, computer systems. EPROM and EEPROM typically comprise a large number of memory cells having electrically isolated gates, referred to as floating gates. Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by program and erase operations, respectively.
Another type of non-volatile memory is flash memory. Flash memory is a derivative of EPROM and EEPROM. Although flash memory shares many characteristics with EPROM and EEPROM, the current generation of flash memory differs in that erase operations are performed in blocks. Flash memories have the potential of replacing hard storage disk drives in computer systems. The advantages would be replacing a complex and delicate mechanical system with a rugged and easily portable small solid-state non-volatile memory system. There is also the possibility that, given their very high potential densities, flash memories might be used to replace DRAMs if certain improvements in operating speed, e.g., in the erase operation, were realized.
A typical flash memory device comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each memory cell includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells in a block can be electrically programmed on a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
Programmable address decode circuits and buffers are needed in conjunction with the memory array to allow faulty rows and/or columns of the array to be replaced by functional redundant rows and/or columns. An example of a redundancy repair scheme is shown in U.S. Pat. No. 5,324,681, issued to Lowrey on Jun. 28, 1994. Another is provided in U.S. Pat. No. 4,051,354, issued to Choate on Sep. 27, 1997. Another is provided in U.S. Pat. No. 5,327,380, issued to Kersh III on Jul. 5, 1994.
With the increasing array density of successive generations of flash memory devices, the desirability of incorporating other functions, such as programmable address decode logic, into the chip also increases. Any successful incorporated technology, however, must be cost competitive with the existing alternative of combining separate chips at the card or package level, each being produced with independently optimized technologies. Any significant addition of process steps to an existing flash memory technology in order to provide added functions, such as high speed logic, static random access memory (SRAM), or EEPROM, becomes rapidly cost prohibitive due to the added process complexity cost and decreased yield. Accordingly, there is a need to provide additional functions on a flash memory chip with little or no modification of the optimized process flow.
Programmable address decode circuits conventionally employ one time programmable (OTP) switches. Fuses and antifuses, present in peripheral circuits, are one method for constructing address decode logic. The fuse or antifuse integrally combines the functions of a switching element, which makes the interconnection, and a programming element, which stores the state of the switching element, i.e., either xe2x80x9coffxe2x80x9d (a blown fuse) or xe2x80x9conxe2x80x9d (an unblown fuse).
Fusible elements are employed in integrated circuits to permit changes in the configuration of the integrated circuits after fabrication. For example, fusible elements can be used to replace defective circuits with redundant circuits. Memory devices are typically fabricated with redundant memory cells. The redundant memory cells may be enabled with fusible elements after fabrication to replace defective memory cells found during a test of fabricated memory devices.
One type of fusible link that can be used is a standard polysilicon fuse. The fuse comprises a polysilicon conductor approximately 0.5xcexcthick that is fabricated on the integrated circuit such that in its normal state there is a complete electrical path through the fuse. To program the fuse, a high power laser is used to open the electrical path by evaporating a portion of the polysilicon. The laser can be used to open selected polysilicon fuses in an integrated circuit to change its configuration. The use of polysilicon fuses, however, is attended by several disadvantages. Polysilicon fuses must be spaced apart from each other in an integrated circuit such that when one of them is being opened by a laser, the other polysilicon fuses are not damaged. A bank of polysilicon fuses therefore occupies a substantial area of an integrated circuit. As integrated circuits continue to be fabricated with high density circuitry, the need for more fusible links also increases. In addition, polysilicon fuses cannot be opened once an integrated circuit is placed in an integrated circuit package, or is encapsulated in any manner.
Another type of fusible link that has been used in integrated circuits is the antifuse. An antifuse comprises two conductive terminals separated by an insulator or a dielectric, and is fabricated as an open circuit. In this respect, the antifuse is electrically opposite of the fuse. To program the antifuse, a high voltage is applied across its terminals to rupture the insulator and form an electrical path between the terminals. One type of antifuse that is commonly used in integrated circuits is an oxide-nitride-oxide (ONO) antifuse. A typical ONO antifuse has a layer of nitride sandwiched between two layers of oxide, where the bottom layer of oxide is in contact with polysilicon and the top layer of oxide is also in contact with polysilicon. The ONO sandwich is a dielectric such that the unprogrammed antifuse functions as a capacitor. To program the ONO antifuse, a large potential is applied across the dielectric such that the dielectric is ruptured and the two polysilicon layers are shorted together.
Antifuses have several advantages that are not available with fuses. A bank of antifuses takes up much less area of an integrated circuit because they are programmed by a voltage difference that can be supplied on wires connected to the terminals of each of the antifuses. The antifuses may be placed close together in the bank, and adjacent antifuses are not at risk when one is being programmed. Antifuses can also be programmed after an integrated circuit is placed in an integrated circuit package, or encapsulated, by applying appropriate signals to pins of the package. This is a significant advantage for several reasons. First, an integrated circuit may be tested after it is in a package, and may then be repaired by replacing defective circuits with redundant circuits by programming selected antifuses. A generic integrated circuit may be tested and placed in a package before it is configured to meet the specifications of a customer. This reduces the delay between a customer order and shipment. The use of antifuses to customize generic integrated circuits also improves the production yield for integrated circuits because the same generic integrated circuit can be produced to meet the needs of a wide variety of customers.
Despite these advantages, the use of antifuses in integrated circuits is limited by a lack of adequate circuitry to support the programming and reading of the antifuses. In addition, another disadvantage with ONO antifuses is that they are fabricated with separate, extra steps when an integrated circuit is fabricated.
Conventional fuses and antifuses also share a number of significant drawbacks that limit their usefulness. One such significant drawback is that neither fuses nor antifuses are reprogrammable. Rather, they are one time programmable devices, making them difficult to test and unsuitable for a large class of applications where reprogrammability is desirable or required. Fuses and antifuses suffer from the further disadvantage of not being fabricated according to the flash memory process flow.
Micron Technology, Inc. taught in U.S. Pat. No. 5,324,681, which issued to Lowrey et al. on Jun. 28, 1994, that one time programmable (OTP) memory cells formed as MOSFETs could be used to replace laser/fuse programmable memory cells for applications such as OTP repair of DRAMs using redundant rows and columns of DRAM memory cells and OTP selection of options on a DRAM (such as fast page mode (FPM) or extended data out (EDO)). One of the key advantages of that capability is the ability to program the OTP memory cells after the DRAM memory chip is packaged, a decided advantage over previous solutions. However, the invention in the Lowrey patent still has the disadvantage of single time programmability.
Another approach to solving the programmable switching problem is described in U.S. Pat. No. 5,764,096, which issued to Lipp et al. on Jun. 9, 1998. U.S. Pat. No. 5,764,096 provides a general-purpose nonvolatile, reprogrammable switch, but does not achieve the same using the commonality in the basic DRAM cell structure. Thus, the Lipp patent does not achieve the desired result of providing nonvolatile memory functions on a DRAM chip with little or no modification of the DRAM process flow.
Still another alternative to programmable interconnects, e.g., logic switching circuits, uses a metal oxide semiconductor field effect transistor (MOSFET) as the switching element. The MOSFET is controlled by the stored memory bit of a programming element. Most commonly, this programming element is a dynamic random access memory (DRAM) cell. Such DRAM based field programmable gate arrays (FPGAs) are reprogrammable and use a DRAM process flow, but have a disadvantage in that the programming of the switching elements is lost whenever power is turned off. A separate, nonvolatile memory cell must be used to store the programmed pattern on power down, and the FPGA must be reprogrammed each time the device is powered back up. This need again increases the fabrication complexity and requires significant additional chip surface space.
Accordingly, a need continues to exist for fuse and antifuse elements that can be reprogrammed and that are compatible with MOSFET memory technology. Such elements should be capable of being fabricated on a MOSFET memory chip with little or no modification of the MOSFET memory process flow.
The above mentioned and other deficiencies are addressed in the following detailed description. According to various implementations of the present invention, p-channel MOSFET devices are used as reprogrammable fuse or antifuse elements in a memory decode circuit by utilizing anomalous hole generation. A sufficiently large negative gate bias voltage is applied to cause tunnel electrons to gain enough energy to exceed the band gap energy of the oxide. As a result, energetic hole-electron pairs are generated in the silicon substrate. The holes are then injected from the substrate into the oxide, where they remain trapped. A large shift in the threshold voltage of the p-channel MOSFET results. The device can subsequently be reset by applying a positive gate bias voltage. Accordingly, particular benefits are realized for applications in which reprogrammability is desired or required. Further, such fuse or antifuse elements can be implemented readily in the context of a MOSFET memory process flow.
According to one embodiment, the present invention is directed to a programmable switch including a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has first and second source/drain regions, a channel region between the first and second source/drain regions, and a gate separated from the channel region by a gate oxide. A wordline is coupled to the gate. A first transmission line is coupled to the first source/drain region. A second transmission line is coupled to the second source/drain region. The MOSFET is a programmed MOSFET having a positive charge trapped in the gate oxide such that a threshold voltage of the MOSFET is significantly altered compared to a threshold voltage of the MOSFET in an unprogrammed state. The switch may be embodied as a fuse or an antifuse.
In another embodiment, a programmable switch includes a p-channel MOSFET in a substrate. The MOSFET has a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a gate oxide. A wordline is coupled to the gate. A sourceline is coupled to the source region. A bitline is coupled to the drain region. The MOSFET is a programmed MOSFET having a positive charge trapped in the gate oxide such that a threshold voltage of the MOSFET is significantly altered compared to a threshold voltage of the MOSFET in an unprogrammed state. The switch may be embodied as a fuse or an antifuse.
Other embodiments of the present invention include integrated circuits, programmable decoders, and electrical systems incorporating the programmable switch.
Still another embodiment is directed to a method for programming a p-channel MOSFET in a substrate into a reprogrammable switch. First and second voltage potentials are applied to source and drain regions, respectively, of the MOSFET. A negative gate potential is applied to a gate region of the MOSFET. Applying the first and second voltage potentials and the negative gate potential causes hot hole injection from the substrate into a gate oxide of the MOSFET.
In another method embodiment for programming a p-channel MOSFET in a substrate into a reprogrammable switch, both source and drain regions of the MOSFET are coupled to ground. A negative gate potential to a gate region of the MOSFET, causing hot hole injection from the substrate into a gate oxide of the MOSFET.
Yet another embodiment is directed to a method for performing address decoding in a memory, including coupling a plurality of address lines and a plurality of output lines to a programmable decoder having a plurality of rows and a plurality of redundant rows. A row is unselected by using hot hole injection to program a programmable switch associated with the row. The programmable switch includes a MOSFET in a substrate. The MOSFET has a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, and a gate separated from the channel region by a gate oxide. The MOSFET is a programmed MOSFET having a positive charge trapped in the gate oxide such that a threshold voltage of the MOSFET is significantly altered compared to a threshold voltage of the MOSFET in an unprogrammed state.
Another method embodiment for performing address decoding in a memory includes writing to a MOSFET associated with a row of the address decoder, thereby causing a positive charge to be trapped in a gate oxide of the MOSFET associated with the row. Writing to the MOSFET associated with the row causes the row to be uncoupled from a row driver. A MOSFET associated with a redundant row of the address decoder is erased by removing a positive charge trapped in a gate oxide of the MOSFET associated with the redundant row. Erasing the MOSFET associated with the redundant row causes the redundant row to be coupled to a redundant row driver.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description that follow more particularly exemplify these embodiments.